
package Fifo

import chisel3._
import chisel3.util._


class Arbiters extends Module{
  val io = IO(new Bundle {
    val in = Flipped(Vec(2, Decoupled(UInt(8.W))))
    val out = Decoupled(UInt(8.W))
  })

  val arbiter = Module(new Arbiter(UInt(8.W), 2))  // 2 to 1 Priority Arbiter
  arbiter.io.in <> io.in
  io.out <> arbiter.io.out

}

object Arbiters_Gen extends App {
  println("Generating the adder hardware")
  (new chisel3.stage.ChiselStage).emitVerilog(new Arbiters(),Array("--target-dir", "generated/ChiselStudy/Arbiters"))
}